
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;

LIBRARY ECE337_IP;

ENTITY TRANSMITTER IS
   PORT( 
        CLK      : IN     std_logic;
        RST_N    : IN     std_logic;
        LOG      : IN     std_logic;
        M_DATA   : IN     std_logic_vector (7 DOWNTO 0);
        R_ERROR  : IN     std_logic;
        W_ENABLE : IN     std_logic;
        FULL     : OUT    std_logic;
        D_MINUS  : OUT    std_logic;
        D_PLUS   : OUT    std_logic
        );
END TRANSMITTER ;


ARCHITECTURE struct OF TRANSMITTER IS

   -- Internal signal declarations
   SIGNAL R_DATA       : std_logic_vector(7 DOWNTO 0);
   SIGNAL D_ORIG       : std_logic;
   SIGNAL EMPTY        : std_logic;
   SIGNAL SHIFT_ENABLE : std_logic;
   SIGNAL R_ENABLE     : std_logic;
   SIGNAL NEWPACKET    : std_logic;
   SIGNAL SHIFT_UPDT   : std_logic;
   SIGNAL CRC_FLAG     : std_logic;

   -- Implicit buffer signal declarations



   -- Component Declarations
   COMPONENT RCV_FIFO  
   PORT (
      CLK      : IN     std_logic;
      R_ENABLE : IN     std_logic;
      RST_N    : IN     std_logic;
      W_DATA   : IN     std_logic_vector (7 DOWNTO 0);
      W_ENABLE : IN     std_logic;
      EMPTY    : OUT    std_logic;
      FULL     : OUT    std_logic;
      R_DATA   : OUT    std_logic_vector (7 DOWNTO 0)
   );
   END COMPONENT;
   COMPONENT ENCODE
   PORT (
      CLK          : IN     std_logic;
      RST_N        : IN     std_logic;
      SHIFT_ENABLE : IN     std_logic;
      D_ORIG       : IN     std_logic;
      EMPTY        : IN     std_logic;
      D_PLUS       : OUT    std_logic;
      D_MINUS      : OUT    std_logic; 
      NEWPACKET    : OUT    std_logic;
      CRC_FLAG     : OUT    std_logic;
      SHIFT_UPDT   : OUT    std_logic
   );
   END COMPONENT;
   COMPONENT TCU
   PORT (
      CLK          : IN     std_logic;
      RST_N        : IN     std_logic;
      SHIFT_ENABLE : IN     std_logic;
      SHIFT_UPDT   : IN     std_logic;
      CRC_FLAG     : IN     std_logic;
      LOG          : IN     std_logic;
      R_ERROR      : IN     std_logic;
      EMPTY        : IN     std_logic;
      R_ENABLE     : OUT    std_logic
   );
   END COMPONENT;
   COMPONENT SHIFTBACK
   PORT (
      CLK          : IN     std_logic;
      RST_N        : IN     std_logic;
      NEWPACKET    : IN     std_logic;
      SHIFT_ENABLE : IN     std_logic;
      RCV_DATA     : IN     std_logic_vector (7 DOWNTO 0);
      SHIFT_UPDT   : IN     std_logic;
      D_ORIG       : OUT    std_logic
   );
   END COMPONENT;
   COMPONENT TX_TIMER
   PORT (
      CLK          : IN     std_logic;
      LOG          : IN     std_logic;
      RST_N        : IN     std_logic;
      SHIFT_ENABLE : OUT    std_logic
   );
   END COMPONENT;


BEGIN

   -- Instance port mappings.
   U_0 : ENCODE
      PORT MAP (
         CLK          => CLK,
         RST_N        => RST_N,
         D_PLUS       => D_PLUS,
         D_MINUS      => D_MINUS,
         SHIFT_ENABLE => SHIFT_ENABLE,
         D_ORIG       => D_ORIG,
         EMPTY        => EMPTY,
         NEWPACKET    => NEWPACKET,
         SHIFT_UPDT   => SHIFT_UPDT,
         CRC_FLAG     => CRC_FLAG
      );
   U_1 : SHIFTBACK
      PORT MAP (
         CLK    => CLK,
         RST_N  => RST_N,
         NEWPACKET    => NEWPACKET,
         SHIFT_ENABLE => SHIFT_ENABLE,
         D_ORIG       => D_ORIG,
         RCV_DATA     => M_DATA,
         SHIFT_UPDT   => SHIFT_UPDT
      );
   U_2 : TCU
      PORT MAP (
         CLK          => CLK,
         RST_N        => RST_N,
         EMPTY        => EMPTY,
         LOG          => LOG,
         R_ERROR      => R_ERROR,
         SHIFT_ENABLE => SHIFT_ENABLE,
         SHIFT_UPDT   => SHIFT_UPDT,
         CRC_FLAG     => CRC_FLAG,
         R_ENABLE     => R_ENABLE
      );
   U_3 : TX_TIMER
      PORT MAP (
         CLK          => CLK,
         RST_N        => RST_N,
         SHIFT_ENABLE => SHIFT_ENABLE,
         LOG          => LOG
      );
   U_4 : RCV_FIFO 
      PORT MAP (
         CLK      => CLK,
         RST_N    => RST_N,
         R_ENABLE => R_ENABLE,
         W_ENABLE => W_ENABLE,
         W_DATA   => M_DATA,
         R_DATA   => R_DATA,
         EMPTY    => EMPTY,
         FULL     => FULL
      );

END struct;
